ODM Semi-Additive Process SAP Service & Manufacturer

Subtractive etching starts with a thick, fully laminated copper foil (e.g., 12μm to 35μm) on a core. The unwanted copper is chemically etched away. Because chemical etchants act isotropically (in all directions equally), the etchant eats sideways while cutting downward, producing an aggressive trapezoidal trace cross-section and severe undercut that caps resolution around 40μm line/space.

Modified Semi-Additive Process (mSAP) begins with an ultra-thin copper foil (typically 2μm to 3μm) bonded to the dielectric. Pattern plating adds copper upward inside photoresist channels, followed by a fast chemical flash etch that strips only the base 2μm seed foil. This yields significantly steeper sidewalls capable of 20μm to 30μm line/space.

Full Semi-Additive Process (SAP) utilizes no starting copper foil whatsoever. An unclad dielectric film (such as Ajinomoto Build-up Film) is catalyzed, and a sub-micron electroless copper seed layer (<0.5μm) is chemically deposited. After photolithography, electrolytic copper grows upward to build traces with true 90-degree vertical sidewalls. Flash-etching the nanometer-thin seed layer causes virtually zero horizontal trace loss, enabling line/space geometries below 12μm and down to 5μm.

At frequencies above 10 GHz, electrical current flows primarily along the outermost perimeter of the conductor due to the skin effect (at 28 GHz, the skin depth of copper is less than 0.4μm). In traditional subtractive circuits, trapezoidal sloping sidewalls and copper tooth roughness (required for mechanical adhesion to resin) introduce massive insertion loss, impedance discontinuities, and phase jitter.

SAP manufactures strictly orthogonal, rectangular cross-sections where the trace width is uniform from the base to the top surface. Furthermore, because SAP deposits copper onto low-roughness advanced dielectric films (Ra < 150 nm), the conductor profile maintains consistent characteristic impedance (typically within ±5% tolerance compared to ±12% in subtractive processes) and eliminates microstrip reflections up to 110 GHz.

When migrating from standard multilayer PCB to SAP IC substrates, CAD rules must reflect microscopic plating tolerances:
1. Avoid Acute Trace Angles: Utilize 45-degree or curvilinear routing rather than 90-degree corners to prevent electrolytic solution pooling and localized over-plating.
2. Copper Density Balancing: SAP is an electroplating process. Highly uneven conductor distributions cause current density variations across the panel, resulting in uneven trace height. Copper thieving grids must be designed systematically on outer layers.
3. Micro-via Aspect Ratio: Laser micro-vias must maintain an aspect ratio (depth to diameter) between 0.7:1 and 0.8:1 to ensure complete, void-free copper filling during the plating stage.
4. Solder Mask Clearance: Standard liquid photoimageable (LPI) soldermask lacks the resolution for sub-20μm pitches. Designs should specify dry-film solder mask or direct photodefinable dielectric layers (PID) with zero solder mask encroachment on critical pads.

The primary reliability risk in SAP is adhesive delamination between the electroless copper seed layer and the low-profile dielectric matrix, as well as micro-cracking at the interface of stacked filled vias during reflow thermal excursions.

We eliminate these failure modes through rigorous process governance: (1) Vacuum atmospheric plasma surface treatment prior to electroless seeding, which increases chemical bond energy without mechanical surface roughening; (2) Closed-loop chemical bath monitoring using cyclic voltammetric stripping (CVS) to preserve ultra-pure copper crystalline structures; and (3) Post-lamination thermal annealing to relieve internal mechanical stress, followed by 100% 3D X-ray (CT scan) and high-stress IST (Interconnect Stress Testing) cycles to IPC-TM-650 standards.

Our Shenzhen production facility combines high-end substrate fabrication with 8 high-speed SMT assembly lines under one roof. Our localized supply chain hub maintains direct direct-factory agreements with leading silicon vendors, authorized component channels, and authorized passives distributors. When you release a turnkey build, we execute synchronized engineering: the SAP substrate build-up occurs simultaneously with automated component kitting, moisture sensitivity baking (MSD), and custom test fixture programming. This compressed pipeline delivers finished, fully tested sub-assemblies in weeks rather than months.